Inductive device

ABSTRACT

An inductive device includes an insulating layer, a lower magnetic layer, and an upper magnetic layer that are formed such that the insulating layer does not separate the lower magnetic layer and the upper magnetic layer at the outer edges or wings of the inductive device. The lower magnetic layer and the upper magnetic layer form a continuous magnetic layer around the insulating layer and the conductors of the inductive device. Magnetic leakage paths are provided by forming openings through the upper magnetic layer. The openings may be formed through the upper magnetic layer by semiconductor processes that have relatively higher precision and accuracy compared to semiconductor processes for forming the insulating layer such as spin coating. This reduces magnetic leakage path variation within the inductive device and from inductive device to inductive device.

RELATED APPLICATION

This application is a division of U.S. patent application Ser. No.17/658,266, filed Apr. 7, 2022, which is a is a continuation of U.S.patent application Ser. No. 16/947,359, filed Jul. 29, 2020 (now U.S.Pat. No. 11,222,576), the contents of which are incorporated herein byreference in their entireties.

BACKGROUND

An inductor is a passive electronic component that is used in variouselectronic applications, such as radio frequency filters, alternatingcurrent (AC) blockers, voltage regulators, transformers, and/or thelike.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIGS. 1A-1C are diagrams of an example inductive device describedherein.

FIGS. 2A-2J are diagrams of one or more example implementationsdescribed herein.

FIG. 3 is a diagram illustrating example performance parametersassociated with a plurality of example inductive devices describedherein.

FIG. 4 is a diagram of an example environment in which systems and/ormethods described herein may be implemented.

FIG. 5 is a diagram of example components of one or more devices of FIG.4 .

FIG. 6 is a flowchart of example process for forming an inductivedevice.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

An inductor may be designed with various parameters of the inductor inmind, such as inductance, magnetic flux, magnetic leakage paths,saturation current, and/or the like. Due to the imprecise nature of somesemiconductor processes such as spin coating, some layers or films of aninductor may result in decreased performance for the inductor. Forexample, an insulating layer of an inductor may be formed by spincoating. The insulating layer may be used for one or more magneticleakage paths between a lower magnetic layer and an upper magnetic layerof the inductor. However, spin coating may result in layer thicknessvariations in the insulating layer from inductor to inductor and/orwithin the same inductor. These layer thickness variations may produceuneven magnetic leakage paths, which may result in inconsistentelectrical performance.

Some implementations described herein provide various inductive devices,such as inductors, coupled inductors, coupled inductor voltageregulators (CLVR), transformers, and/or other types of inductivedevices. As further disclosed herein, an inductive device may include aninsulating layer, a lower magnetic layer, and an upper magnetic layerthat are formed such that the insulating layer does not separate thelower magnetic layer and the upper magnetic layer at the outer edges orwings of the inductive device. The lower magnetic layer and the uppermagnetic layer form a continuous magnetic layer around the insulatinglayer and the conductors of the inductive device. Magnetic leakage pathsare provided for the inductive device by forming openings in the uppermagnetic layer instead of through the formation of the insulating layer.The openings may be formed in the upper magnetic layer by semiconductorprocesses that have relatively higher precision and accuracy compared tosemiconductor processes for forming the insulating layer such as spincoating. This reduces magnetic leakage path variation within theinductive device and from inductive device to inductive device.Moreover, performance characteristics of the inductive device can betuned based on the configuration and/or parameters of the openings inthe upper magnetic layer to achieve desired and/or optimal inductorperformance.

FIGS. 1A-1C are diagrams of one or more examples of an inductive device100 described herein. Inductive device 100 may be and/or include varioustypes of inductive devices, such as an inductor, a coupled inductor, aCLVR, a transformer, and/or another type of inductive device. FIG. 1Aillustrates a perspective view of an example of inductive device 100.FIG. 1B illustrates a perspective view of another example of inductivedevice 100. FIG. 1C illustrates a cross-sectional view of inductivedevice along line X-X shown in FIG. 1A. As shown in FIGS. 1A-1C,inductive device 100 may include various components, such as aninsulating layer 102, one or more conductors 104, another insulatinglayer 106, a magnetic layer 108, and one or more openings 110. In someimplementations, inductive device 100 includes more components, fewercomponents, and/or differently configured components than thoseillustrated in FIGS. 1A-1C.

Insulating layers 102 and 106 may be formed of one or more insulatingand/or dielectric materials, such as silicon mononitride (SiN), silicondioxide (SiO), polyimide, benzocyclobutene, and/or the like. Insulatinglayers 102 and 106 may insulate conductor(s) 104 from magnetic layer108. Conductor(s) 104 may include one or more conductive traces,conductive wires, and/or other conductive members of inductive device100. Conductor(s) 104 may be formed of one or more conductive materials,such as copper, gold, silver, and/or the like. In some implementations,inductive device 100 includes two or more conductors 104, which maycorrespond to an input of inductive device 100 (e.g., V_(in)) and anoutput from inductive device 100 (e.g., V_(out)). Magnetic layer 108 maybe formed of one or more magnetic materials, such as a cobalt alloy(e.g., cobalt-zirconium-tantalum (CoZrTa) and/or the like), a nickelalloy (e.g., nickel-iron (NiFe) and/or the like), and/or anothermagnetic material.

One or more openings 110 may be formed in and/or through magnetic layerto insulating layer 106. Opening(s) 110 provide one or more magneticleakage paths for inductive device 100. As shown in FIGS. 1A and 1B,opening(s) 110 may have various attributes, such as various sizes,shapes, configurations, spacings, patterns, quantities, and/or the like.In some implementations, the attributes of opening(s) 110 are based onone or more performance parameters to be achieved and/or satisfied forinductive device 100, such as a maximum inductance or initialinductance, a saturation current, and/or the like.

As shown in FIG. 1A, opening(s) 110 may include one or more holes inand/or through magnetic layer 108 to insulating layer 106. In someimplementations, inductive device 100 includes a single hole in and/orthrough magnetic layer 108 to insulating layer 106. In someimplementations, inductive device 100 includes a plurality of holes inand/or through magnetic layer 108 to insulating layer 106. The depth ofopening(s) 110 may be equal to or greater than the thickness of magneticlayer 108 such that opening(s) 110 are formed completely throughmagnetic layer 108. In some implementations, opening(s) 110 are formedin and/or through magnetic layer 108 at a top of inductive device 100,are formed in and/or through magnetic layer 108 at a bottom of inductivedevice 100, and/or are formed in and/or through magnetic layer 108 atanother location on inductive device 100. In some implementations, theplurality of holes are the same size (e.g., the same diameter), the sameshape (e.g., circle, oval, square, rectangle, or another shape), and/orthe like. In some implementations, two or more holes of the plurality ofholes are of a different size, a different shape, and/or the like. Insome implementations, the spacing between the plurality of holes is thesame spacing. In some implementations, the spacing between at least asubset of the plurality of holes are different spacing distances.

As further shown in FIG. 1A, the plurality of holes (e.g., openings 110)may be configured into a plurality of subsets of holes, where eachsubset of holes is positioned over a respective conductor 104. In someimplementations, each subset of holes includes the same quantity ofholes. In some implementations, two or more subsets of holes includedifferent quantities of holes. In some implementations, the holes withina particular subset of holes are the same size, are the same shape, havethe same spacing, and/or the like. In some implementations, two or moreholes within a particular subset of holes are different sizes, aredifferent shapes, have different spacings, and/or the like.

As shown in FIG. 1B, opening(s) 110 may include one or more trenches inand/or through magnetic layer 108 to insulating layer 106. In someimplementations, inductive device 100 includes a single trench in and/orthrough magnetic layer 108 to insulating layer 106. In someimplementations, inductive device 100 includes a plurality of trenchesin and/or through magnetic layer 108 to insulating layer 106. Each ofthe plurality of trenches may have a width, a length, and a depth. Thedepth of each trench may be equal to or greater than the thickness ofmagnetic layer 108 such that each trench is completely through magneticlayer 108. In some implementations, the width of a trench is the samealong the length of the trench. In some implementations, the width of atrench varies along the length of the trench. In some implementations,the length of a trench spans the entire length (or substantially spanthe entire length) of magnetic layer 108. In some implementations, thelength of a trench spans a subset of the entire length of magnetic layer108. In some implementations, the plurality of trenches are the samewidth, the same length, and/or the like. In some implementations, two ormore trenches of the plurality of trenches are different widths, adifferent lengths, and/or the like.

As further shown in FIG. 1B, in some implementations, the plurality oftrenches (e.g., openings 110) may be configured such that each of theplurality of trenches is positioned over a respective conductor 104. Insome implementations, the plurality of trenches are configured into aplurality of subsets of trenches. In these cases, each subset mayinclude one or more trenches that are positioned over a respectiveconductor 104. In some implementations, the plurality of subsets oftrenches include the same quantity of trenches, the same width oftrenches, the same length of trenches, and/or the like. In someimplementations, two or more subsets of trenches include differentquantities of trenches, different width of trenches, different length oftrenches, and/or the like.

In some implementations, if a subset of the plurality of trenchesincludes two or more trenches (e.g., that each span a subset of theentire length of magnetic layer 108), the trenches within the subset maybe the same width, the same shape, and/or the like. In someimplementations, if a subset of the plurality of trenches includes twoor more trenches (e.g., that each span a subset of the entire length ofmagnetic layer 108), the trenches within the subset may be differentwidths, different lengths, and/or the like.

In some implementations, opening(s) 110 may include a combination of oneor more holes and one or more trenches in and/or through magnetic layer108 to insulating layer 106. In other words, opening(s) may include acombination of one or more holes as shown in FIG. 1A and one or moretrenches as shown in FIG. 1B. The attributes of the one or more holesand/or the attributes of the one or more trenches may be selected basedon one or more performance parameters to be achieved and/or satisfiedfor inductive device 100.

While FIGS. 1A and 1B provide some example configurations of opening(s)110, other example configurations may be formed in magnetic layer 108 toprovide one or more magnetic leakage paths for inductive device 100. Forexample, opening(s) 110 may include one or more holes and one or moretrenches, may include various combinations of holes and/or trenches, theholes and/or trenches may have various sizes, shapes, spacings,placement, quantity, and/or other parameters.

As shown in FIG. 1C, magnetic layer 108 surrounds and/or enclosesinsulating layer 102, conductor(s) 104, and insulating layer 106 exceptwhere opening(s) 110 are formed in and/or through magnetic layer 108.Magnetic layer 108 may be formed during manufacturing of inductivedevice 100 from a lower magnetic layer and an upper magnetic layer. Thelower magnetic layer and the upper magnetic layer may connect in one ormore wings or edges 112 of inductive device 100 such that insulatinglayer 102 is not exposed through magnetic layer 108 in wing(s) oredge(s) 112. Wing(s) or edge(s) 112 may provide one or more regions inwhich the upper magnetic layer may be formed on one or more portions ofthe lower magnetic layer after formation of insulating layer 102,conductor(s) 104, and insulating layer 106. Example dimensions ofwing(s) or edge(s) 112 include a 10 μm height and a 10 μm width.However, other dimensions may be used for wing(s) or edge(s) 112.

In some implementations, an electrical current flows throughconductor(s) 104 to generate magnetic flux, which may be enhancedthrough the use of magnetic layer 108. Surrounding and/or enclosing thecomponents of inductive device 100 with magnetic layer 108 confines themagnetic flux to increase the inductance of inductive device 100.Opening(s) 110 in and/or through magnetic layer 108 provide one or moremagnetic leakage paths for the magnetic flux to increase the saturationcurrent of inductive device 100. Moreover, opening(s) 110 may be formedin and/or through magnetic layer 108 by one or more semiconductorprocesses that are highly accurate, precise, and repeatable, such asforming opening(s) 110 in and/or through magnetic layer 108 by using oneor more of a lithography process and/or an etching process. In this way,defects and/or variations in size and/or shape between opening(s) 110(and thus, magnetic leakage paths) of inductive device 100, and frominductive device 100 to other inductive devices, are reduced to provideconsistent performance.

As indicated above, FIGS. 1A-1C are provided as one or more examples.Other examples may differ from what is described with regard to FIGS.1A-1C.

FIGS. 2A-2J are diagrams of one or more example implementations 200described herein. Example implementation(s) 200 illustrate one or moreexample techniques of forming an inductive device such as inductivedevice 100. In some implementations, the one or more example techniquesmay be used to form other inductive devices. In some implementations,other techniques and/or differently ordered techniques may be used toform inductive device 100 and/or other inductive devices.

As shown in FIG. 2A, example implementation(s) 200 may include forminglower magnetic layer 108 a (block 202), forming insulating layer 102(block 204), removing one or more portions x of insulating layer 102(block 206), forming conductor(s) 104 (block 208), forming insulatinglayer 106 (block 210), forming upper magnetic layer 108 b (block 212),forming a photoresist layer 216 (block 214), removing one or moreportions of photoresist layer 216 to form a pattern 220 (block 218),removing one or more portions of upper magnetic layer 108 b to formopening(s) 110 (block 220), and removing the remaining portions ofphotoresist layer 216 (block 224).

As shown in FIG. 2B, at block 202, a semiconductor processing device(e.g., one or more of the semiconductor processing devices illustratedand described below in connection with FIG. 4 ) forms a lower magneticlayer 108 a. In some implementations, the semiconductor processingdevice forms lower magnetic layer 108 a on a substrate 226 such as asemiconductor wafer or a layer of a semiconductor wafer. In someimplementations, the semiconductor processing device forms lowermagnetic layer 108 a using various semiconductor processing techniques,such as chemical vapor deposition (e.g., epitaxial growing and/or thelike), physical vapor deposition (e.g., sputtering and/or the like),plating (e.g., electroplating and/or the like), and/or the like.

As further shown in FIG. 2B, at block 204, a semiconductor processingdevice (e.g., one or more of the semiconductor processing devicesillustrated and described below in connection with FIG. 4 ) formsinsulating layer 102 on lower magnetic layer 108 a. In someimplementations, the semiconductor processing device forms insulatinglayer 102 using a coating technique such as a spin coating technique.The spin coating technique may include depositing an amount ofdielectric material onto lower magnetic layer 108 a and rotating orspinning the wafer on which lower magnetic layer 108 a is formed todistribute the dielectric material across lower magnetic layer 108 a toform insulating layer 102.

As shown in FIG. 2C, at block 206, a semiconductor processing device(e.g., one or more of the semiconductor processing devices illustratedand described below in connection with FIG. 4 ) removes one or moreportions of insulating layer 102 (indicated by x in FIG. 2C). Forexample, a semiconductor processing device may form a photoresist layeron insulating layer 102, a semiconductor processing device may exposethe photoresist layer to a radiation source to pattern the photoresistlayer, a semiconductor processing device may develop and remove portionsof the photoresist layer to expose the pattern, a semiconductorprocessing device may etch the one or more portions of insulating layer102 to remove the one or more portions from lower magnetic layer 108 a,and a semiconductor processing device may remove the remaining portionsof the photoresist layer after etching insulating layer 102 (e.g., usinga chemical stripper and/or another technique). In some examples, thewidth of the one or more portions (e.g., the width of x) is 10 μm. Inother examples, other widths of the one or more portions (e.g., thewidth of x) are removed.

As shown in FIG. 2D, at block 208, a semiconductor processing device(e.g., one or more of the semiconductor processing devices illustratedand described below in connection with FIG. 4 ) forms conductor(s) 104on insulating layer 102. In some implementations, the semiconductorprocessing device forms conductor(s) 104 on insulating layer 102 usingvarious semiconductor processing techniques. For example, thesemiconductor processing device may form conductor(s) 104 using achemical vapor deposition process (e.g., epitaxial growing and/or thelike), a physical vapor deposition process (e.g., sputtering and/or thelike), a plating process (e.g., electroplating and/or the like), orusing another processing technique. In some implementations, asemiconductor processing device polishes or planarize conductor(s) 104after formation of conductor(s) 104. Moreover, if a pattern in aphotoresist layer is used to form conductor(s) 104, a semiconductorprocessing device may remove the remaining portions of the photoresistlayer after formation of conductor(s) 104.

As shown in FIG. 2E, at block 210, a semiconductor processing device(e.g., one or more of the semiconductor processing devices illustratedand described below in connection with FIG. 4 ) forms insulating layer106. For example, the semiconductor processing device may forminsulating layer 106 above lower magnetic layer 108 a, insulating layer102, and conductor(s) 104 such that insulating layer 106 is formed onand/or over one or more portions of insulating layer 102 and/or one ormore portions of conductor(s) 104. In some implementations, thesemiconductor processing device forms insulating layer 106 using acoating technique such as a spin coating technique. The spin coatingtechnique may include depositing an amount of dielectric material ontoinsulating layer 102 and conductor(s) 104, and rotating or spinning thewafer on which lower magnetic layer 108 a is formed to distribute thedielectric material across insulating layer 102 and conductor(s) 104 toform insulating layer 106. In some implementations, insulating layer 102and insulating layer 106 form a single and/or unified insulating layerof inductive device 100.

As shown in FIG. 2F, at block 212, a semiconductor processing device(e.g., one or more of the semiconductor processing devices illustratedand described below in connection with FIG. 4 ) forms an upper magneticlayer 108 b. In some implementations, the semiconductor processingdevice forms upper magnetic layer 108 b above lower magnetic layer 108a, insulating layer 102, conductor(s) 104, and insulating layer 106 suchthat upper magnetic layer 108 b is formed on and/or over one or moreportions of lower magnetic layer 108 a (e.g., one or more portions inedge(s) 112 of inductive device 100) and one or more portions ofinsulating layer 106. In these cases, the ends of upper magnetic layer108 b contacts the ends of lower magnetic layer 108 a to form wings oredge(s) 112 of inductive device 100. As a result, any gaps between theends of lower magnetic layer 108 a and upper magnetic layer 108 b in thewings or edge(s) 122 are closed to form a continuous magnetic layer 108around inductive device 100. Accordingly, magnetic layer 108 surroundsinsulating layer 102, conductor(s) 104, and insulating layer 106. Insome implementations, the semiconductor processing device forms uppermagnetic layer 108 b using various semiconductor processing techniques,such as chemical vapor deposition (e.g., epitaxial growing and/or thelike), physical vapor deposition (e.g., sputtering and/or the like),plating (e.g., electroplating and/or the like), or another semiconductorprocessing technique. Moreover, a semiconductor processing device maypolish or planarize upper magnetic layer 108 b after formation of uppermagnetic layer 108 b.

As shown in FIG. 2G, at block 214, a semiconductor processing device(e.g., one or more of the semiconductor processing devices illustratedand described below in connection with FIG. 4 ) forms a photoresistlayer 216. In some implementations, the semiconductor processing deviceforms photoresist layer 216 on and/or around upper magnetic layer 108 b.Photoresist layer 216 may include a layer of radiation sensitivematerial capable of being patterned via exposure to a radiation source.In some implementations, the semiconductor processing device formsphotoresist layer 216 using a coating technique such as a spin coatingtechnique. The spin coating technique may include depositing an amountof photoresist material onto upper magnetic layer 108 b, and rotating orspinning the wafer on which lower magnetic layer 108 a is formed todistribute the photoresist material across upper magnetic layer 108 b toform photoresist layer 216.

As shown in FIG. 2H, at block 218, a semiconductor processing device(e.g., one or more of the semiconductor processing devices illustratedand described below in connection with FIG. 4 ) removes one or moreportions of photoresist layer 216 to form a pattern 220 in photoresistlayer 216. For example, a semiconductor processing device may expose thephotoresist layer 216 to a radiation source to transfer pattern 220 froma photomask to photoresist layer 216, and a semiconductor processingdevice may develop and remove the one or more portions of photoresistlayer 216 to expose pattern 220. The remaining portions of photoresistlayer 216 may form one or more openings in photoresist layer 216 thatmay be used to form opening(s) 110 through upper magnetic layer 118 b.In some implementations, the size, shape, and/or configuration of theone or more portions removed from photoresist layer 216 to form pattern220 are based on the size, shape, configuration, and/or quantity ofopening(s) 110 to be formed in upper magnetic layer 118 b.

As shown in FIG. 2I, at block 222, a semiconductor processing device(e.g., one or more of the semiconductor processing devices illustratedand described below in connection with FIG. 4 ) removes one or moreportions of upper magnetic layer 108 b to form opening(s) 110. Forexample, the semiconductor processing device may form opening(s) 110 inand/or through upper magnetic layer 108 b to insulating layer 106 toprovide one or more magnetic leakage paths for inductive device 100(e.g., for conductor(s) 104). In some implementations, the semiconductorprocessing device etches opening(s) 110 in and/or through upper magneticlayer 108 b using a wet etching technique, using a dry etchingtechnique, and/or the like. In some implementations, the semiconductorprocessing device etches opening(s) 110 in and/or through upper magneticlayer 108 b based on pattern 220 in photoresist layer 216. For example,the semiconductor processing device may etch opening(s) 110 in and/orthrough upper magnetic layer 108 b in the one or more portions removedfrom photoresist layer 216 to form pattern 220. In some aspects, thesemiconductor processing device forms opening(s) 110 through theportion(s) of upper magnetic layer 108 b such that the opening(s) 110are above conductor(s) 104. In some aspects, the semiconductorprocessing device forms opening(s) 110 through the portion(s) of uppermagnetic layer 108 b such that the opening(s) 110 are positioned to theside(s) of conductor(s) 104 or at other locations relative toconductor(s) 104.

As shown in FIG. 2J, at block 224, a semiconductor processing device(e.g., one or more of the semiconductor processing devices illustratedand described below in connection with FIG. 4 ) removes the remainingportions of photoresist layer 216. For example, the semiconductorprocessing device may use one or more solvents and/or other types ofchemicals to remove or strip the remaining portions of photoresist layer216 from upper magnetic layer 108 b. The remaining portions ofphotoresist layer 216 may be removed after opening(s) 110 are etched inand/or through upper magnetic layer 108 b.

As indicated above, FIGS. 2A-2J are provided as one or more examples.Other examples may differ from what is described with regard to FIGS.2A-2J. As an example, in addition and/or alternatively to formingopening(s) 110 in upper magnetic layer 108 b using the techniquesillustrated and described in connection with reference numbers 214-224,opening(s) 110 may be formed in lower magnetic layer 108 a, may beformed in different locations in upper magnetic layer 108 b, and/orlower magnetic layer 108 a, and/or the like.

FIG. 3 is a diagram illustrating example performance parametersassociated with a plurality of example inductive devices describedherein.

As shown in FIG. 3 , the plurality of example inductive devices (e.g.,inductive device 302, inductive device 304, and inductive device 306)may have different performance parameters based on the magnetic leakagepaths (or lack of magnetic leakage paths) included in the plurality ofinductive devices. The performance parameters may include an inductanceand a saturation current (I_(sat)). The inductance may be a maximuminductance or an initial inductance in nanohenrys (nH) at a low-end orminimum operating current of an inductive device in amps (A). Thesaturation current may be an operating current at which the inductanceof an inductive device drops below a particular inductive level or dropsto a particular percentage (e.g., 80% or another percentage) of themaximum inductance or the initial inductance of the inductive device.

As shown in FIG. 3 , inductive device 302 is formed with no openingsand, thus, no magnetic leakage paths for inductive device 302. As shown,the graph of performance parameters for inductive device 302, exhibits arelatively large maximum inductance or initial inductance. However, dueto the lack of magnetic leakage paths, inductive device 302 exhibits arelatively quick drop in inductance as operating current increases,which corresponds to a relatively low saturation current (e.g.,I_(sat)=0.5 A).

As further shown in FIG. 3 , opening(s) can be added through one or moremagnetic layers of an inductive device to provide magnetic leakagepath(s), which may increase saturation current at the expense of maximuminductance or initial inductance. For example, inductive device 304(which may be an example implementation of inductive device 100) mayinclude openings in the form of holes having a 0.5 μm diameter. As shownin the graph illustrated in FIG. 3 , the 0.5 μm diameter holes throughthe magnetic layer (e.g., the upper magnetic layer) of inductive device304 increases the saturation current of inductive device 304 toI_(sat)=0.8 A relative to inductive device 302, while decreasing themaximum inductance or the initial inductance of inductive device 304relative to inductive device 302. As another example, inductive device306 (which may be another example implementation of inductive device100) may include openings in the form of holes having a 3 μm diameter.As shown in the graph illustrated in FIG. 3 , the 3 μm diameter holesthrough the magnetic layer (e.g., the upper magnetic layer) of inductivedevice 306 increases the saturation current of inductive device 304 toI_(sat)=1.4 A relative to inductive device 302, while decreasing themaximum inductance or the initial inductance of inductive device 304relative to inductive device 302.

Accordingly, the opening(s) through one or more magnetic layers of aninductive device can be configured for various applications and/oroperating environments of the inductive device, to satisfy one or moredesign goals of the inductive device, to satisfy one or more performanceparameters (e.g., to satisfy a maximum inductance or initial inductancethreshold, to satisfy a saturation current threshold, and/or the like),and/or the like. Moreover, the saturation current of an inductive devicemay be more difficult to control relative to the maximum inductance orthe initial inductance of the inductive device, and other parameters ofan inductive device may be adjusted or configured to increase maximuminductance or initial inductance while providing a suitable saturationcurrent through the use of openings in one or more magnetic layers ofthe inductive device. For example, the maximum inductance or the initialinductance of the inductive device may be increased by adjusting thelength of the inductive device, by adjusting the thickness of the one ormore magnetic layers, and/or the like.

As indicated above, FIG. 3 is provided as one or more examples. Otherexamples may differ from what is described with regard to FIG. 3 .

FIG. 4 is a diagram of an example environment 400 in which systemsand/or methods described herein may be implemented. As shown in FIG. 4 ,environment 400 may include a plurality of semiconductor processingdevices 402-416 and a wafer/die transport device 418. The plurality ofsemiconductor processing devices 402-416 may include a coating device402, an exposure device 404, a developer device 406, a plating device408, a deposition device 410, an etching device 412, a polishing device414, a removal device 416, and/or other the like. The devices includedin example environment 400 may be included in a semiconductor cleanroom, a semiconductor foundry, a semiconductor processing and/ormanufacturing facility, and/or the like.

Coating device 402 includes one or more devices capable of formingvarious types of layers on a substrate by a spin coating process oranother type of coating process. For example, coating device 402 mayform one or more insulating layers (e.g., insulating layer 102,insulating layer 106, and/or the like), may form a photoresist layer(e.g., photoresist layer 216), and/or the like as described herein.Photoresist layer 216 may include a layer of radiation sensitivematerial capable of being patterned via exposure to a radiation source,such as an ultraviolet light (UV) source (e.g., a deep UV light source,an extreme UV light source, and/or the like), an x-ray source, and/orthe like.

Exposure device 404 includes one or more devices capable of exposing aphotoresist layer (e.g., photoresist layer 216) to a radiation source,such as an ultraviolet light (UV) source (e.g., a deep UV light source,an extreme UV light source, and/or the like), an x-ray source, and/orthe like. Exposure device 404 may expose the photoresist layer to theradiation source to transfer a pattern from a photomask to thephotoresist layer. The pattern may include one or more semiconductordevice layer patterns for forming one or more semiconductor devices, mayinclude a pattern for forming openings (e.g., openings 110) in aninductive device (e.g., inductive device 100), and/or the like. In someimplementations, exposure device 404 is a scanner, a stepper, or asimilar type of exposure device.

Developer device 406 includes one or more devices capable of developinga photoresist layer (e.g., photoresist layer 216) that has been exposedto a radiation source to develop a pattern transferred to thephotoresist layer from exposure device 404. In some implementations,developer device 406 develops the pattern by removing unexposed portionsof the photoresist layer. In some implementations, developer device 406develops the pattern by removing exposed portions of the photoresistlayer. In some implementations, developer device 406 develops thepattern by dissolving exposed or unexposed portions of the photoresistlayer through the use of a chemical developer.

Plating device 408 includes one or more devices capable of plating asubstrate or a portion thereof with one or more metals. For example,plating device 408 may include a copper electroplating device, analuminum electroplating device, a nickel electroplating device, a tinelectroplating device, a compound material or alloy (e.g., tin-silver,tin-lead, and/or the like) electroplating device, and/or anelectroplating device for one or more other types of conductivematerials, metals, and/or the like. In some implementations, platingdevice 408 is capable of forming one or more conductors (e.g.,conductor(s) 104), one or more magnetic layers (e.g., magnetic layer 108a, magnetic layer 108 b, and/or the like), and/or the like as describedherein.

Deposition device 410 includes one or more devices capable of depositingvarious types of materials onto a substrate. For example, depositiondevice 410 may include a chemical vapor deposition device (e.g., anelectrostatic spray device, an epitaxy device, and/or another type ofchemical vapor deposition device), a physical vapor deposition device(e.g., a sputtering device and/or another type of physical vapordeposition device), and/or the like. In some implementations, depositiondevice 410 deposits a magnetic layer (e.g., lower magnetic layer 108 a,upper magnetic layer 108 b, and/or the like) of an inductive device(e.g., inductive device 100), deposits a metal material to form one ormore conductors (e.g., conductor(s) 104) of the inductive device, and/orthe like as described herein.

Etching device 412 includes one or more devices capable of etchingvarious types of materials. For example, etching device 412 may includea wet etching device, a dry etching device, and/or the like. In someimplementations, etching device 412 etches one or more openings in amagnetic layer (e.g., upper magnetic layer 108 b) of an inductive device(e.g., inductive device 100), etches one or more portions of aninsulating layer (e.g., insulating layer 102) of the inductive device,and/or the like as described herein.

Polishing device 414 includes one or more devices capable of polishingor planarizing various layers of an inductive device (e.g., inductivedevice 100). For example, polishing device 414 may include a chemicalmechanical polishing device and/or another type of polishing device. Insome implementations, polishing device 414 polishes or planarize a layerof deposited or plated material as part of the formation of one or moreconductors (e.g., conductor(s) 104) of the inductive device, one or moremagnetic layers (e.g., lower magnetic layer 108 a, upper magnetic layer108 b, and/or the like) of the inductive device, and/or the like.

Removal device 416 includes one or more devices capable of removing orstripping a photoresist layer (e.g., photoresist layer 216). In someimplementations, removal device 416 is capable of using one or moresolvents and/or other types of chemicals to remove or strip thephotoresist layer from one or more other layers after the photoresistlayer has been exposed to a radiation source by exposure device 404 andused to form a pattern in one or more other layers.

Wafer/die transport device 418 includes a mobile robot, a robot arm, atram or rail car, and/or another type of device that are used totransport wafers and/or dies between semiconductor processing devices402-416 and/or to and from other locations such as a wafer rack, astorage room, and/or the like. In some implementations, wafer/dietransport device 418 is a programmed device to travel a particular path,operates semi-autonomously, or operates autonomously.

The number and arrangement of devices shown in FIG. 4 are provided asone or more examples. In practice, there may be additional devices,fewer devices, different devices, or differently arranged devices thanthose shown in FIG. 4 . Furthermore, two or more devices shown in FIG. 4may be implemented within a single device, or a single device shown inFIG. 4 may be implemented as multiple, distributed devices.Additionally, or alternatively, a set of devices (e.g., one or moredevices) of environment 400 may perform one or more functions describedas being performed by another set of devices of environment 400.

FIG. 5 is a diagram of example components of a device 500. In someimplementations, coating device 402, exposure device 404, developerdevice 406, plating device 408, deposition device 410, etching device412, polishing device 414, removal device 416, and/or wafer/dietransport device 418 includes one or more devices 500 and/or one or morecomponents of device 500. As shown in FIG. 5 , device 500 may include abus 510, a processor 520, a memory 530, a storage component 540, aninput component 550, an output component 560, and a communicationinterface 570.

Bus 510 includes a component that permits communication among multiplecomponents of device 500. Processor 520 is implemented in hardware,firmware, and/or a combination of hardware and software. Processor 520is a central processing unit (CPU), a graphics processing unit (GPU), anaccelerated processing unit (APU), a microprocessor, a microcontroller,a digital signal processor (DSP), a field-programmable gate array(FPGA), an application-specific integrated circuit (ASIC), or anothertype of processing component. In some implementations, processor 520includes one or more processors capable of being programmed to perform afunction. Memory 530 includes a random access memory (RAM), a read onlymemory (ROM), and/or another type of dynamic or static storage device(e.g., a flash memory, a magnetic memory, and/or an optical memory) thatstores information and/or instructions for use by processor 520.

Storage component 540 stores information and/or software related to theoperation and use of device 500. For example, storage component 540 mayinclude a hard disk (e.g., a magnetic disk, an optical disk, and/or amagneto-optic disk), a solid state drive (SSD), a compact disc (CD), adigital versatile disc (DVD), a floppy disk, a cartridge, a magnetictape, and/or another type of non-transitory computer-readable medium,along with a corresponding drive.

Input component 550 includes a component that permits device 500 toreceive information, such as via user input (e.g., a touch screendisplay, a keyboard, a keypad, a mouse, a button, a switch, and/or amicrophone). Additionally, or alternatively, input component 550 mayinclude a component for determining location (e.g., a global positioningsystem (GPS) component) and/or a sensor (e.g., an accelerometer, agyroscope, an actuator, another type of positional or environmentalsensor, and/or the like). Output component 560 includes a component thatprovides output information from device 500 (via, e.g., a display, aspeaker, a haptic feedback component, an audio or visual indicator,and/or the like).

Communication interface 570 includes a transceiver-like component (e.g.,a transceiver, a separate receiver, a separate transmitter, and/or thelike) that enables device 500 to communicate with other devices, such asvia a wired connection, a wireless connection, or a combination of wiredand wireless connections. Communication interface 570 may permit device500 to receive information from another device and/or provideinformation to another device. For example, communication interface 570may include an Ethernet interface, an optical interface, a coaxialinterface, an infrared interface, a radio frequency (RF) interface, auniversal serial bus (USB) interface, a Wi-Fi interface, a cellularnetwork interface, and/or the like.

Device 500 may perform one or more processes described herein. Device500 may perform these processes based on processor 520 executingsoftware instructions stored by a non-transitory computer-readablemedium, such as memory 530 and/or storage component 540. As used herein,the term “computer-readable medium” refers to a non-transitory memorydevice. A memory device includes memory space within a single physicalstorage device or memory space spread across multiple physical storagedevices.

Software instructions may be read into memory 530 and/or storagecomponent 540 from another computer-readable medium or from anotherdevice via communication interface 570. When executed, softwareinstructions stored in memory 530 and/or storage component 540 may causeprocessor 520 to perform one or more processes described herein.Additionally, or alternatively, hardware circuitry may be used in placeof or in combination with software instructions to perform one or moreprocesses described herein. Thus, implementations described herein arenot limited to any specific combination of hardware circuitry andsoftware.

The number and arrangement of components shown in FIG. 5 are provided asan example. In practice, device 500 may include additional components,fewer components, different components, or differently arrangedcomponents than those shown in FIG. 5 . Additionally, or alternatively,a set of components (e.g., one or more components) of device 500 mayperform one or more functions described as being performed by anotherset of components of device 500.

FIG. 6 is a flow chart of an example process 600 associated with formingan inductive device. In some implementations, one or more process blocksof FIG. 6 are performed by one or more semiconductor processing devices(e.g., coating device 402, exposure device 404, developer device 406,plating device 408, deposition device 410, etching device 412, polishingdevice 414, removal device 416, and/or the like). Additionally, oralternatively, one or more process blocks of FIG. 6 may be performed byone or more components of a device 500, such as processor 520, memory530, storage component 540, input component 550, output component 560,communication interface 570, and/or the like.

As shown in FIG. 6 , process 600 may include removing one or moreportions of a first insulating layer of an inductive device from a firstmagnetic layer of the inductive device (block 610). For example, the oneor more semiconductor processing devices may remove one or more portionsof a first insulating layer (e.g., insulating layer 102) of an inductivedevice (e.g., inductive device 100) from a first magnetic layer (e.g.,lower magnetic layer 108 a) of the inductive device, as described above.

As further shown in FIG. 6 , process 600 may include forming a secondmagnetic layer (108 b) of the inductive device on one or more portionsof the first magnetic layer, where the one or more portions of the firstinsulating layer were removed, where the second magnetic layer is formedover the first insulating layer, a second insulating layer of theinductive device, and one or more conductors of the inductive device(block 620). For example, the one or more semiconductor processingdevices may form a second magnetic layer (e.g., upper magnetic layer 108b) of the inductive device on one or more portions of the first magneticlayer, as described above. In some implementations, the one or moreportions of the first insulating layer were removed. In someimplementations, the second magnetic layer is formed over the firstinsulating layer, a second insulating layer (e.g., insulating layer 106)of the inductive device, and one or more conductors (e.g., conductor(s)104) of the inductive device.

As further shown in FIG. 6 , process 600 may include removing one ormore portions of the second magnetic layer to form one or more openingsin the second magnetic layer, wherein the one or more openings provideone or more magnetic leakage paths for the inductive device (block 630).For example, the one or more semiconductor processing devices may removeone or more portions of the second magnetic layer to form one or moreopenings (e.g., opening(s) 110) in the second magnetic layer, asdescribed above. In some implementations, the one or more openingsprovide one or more magnetic leakage paths for the inductive device.

Process 600 may include additional implementations, such as any singleimplementation or any combination of implementations described belowand/or in connection with one or more other processes describedelsewhere herein.

In a first implementation, removing the one or more portions of thesecond magnetic layer includes forming a photoresist layer (photoresistlayer 216) on the second magnetic layer; patterning the photoresistlayer, and etching, after patterning the photoresist layer, the one ormore portions of the second magnetic layer using the photoresist. In asecond implementation, alone or in combination with the firstimplementation, process 600 includes forming the one or more conductorson the insulating layer, forming the second insulating layer on thefirst insulating layer and the one or more conductors, and forming thesecond magnetic layer to cover the second insulating layer and the oneor more portions of the first magnetic layer.

In a third implementation, alone or in combination with one or more ofthe first and second implementations, removing the one or more portionsof the second magnetic layer includes determining, based on one or moreperformance parameters for the inductive device, at least one of arespective shape for each of the one or more openings, a respective sizefor each of the one or more openings, or a respective location in thesecond magnetic layer for each of the one or more openings, and removingthe one or more portions of the second magnetic layer to form the one ormore openings based on the at least one of the respective shape for eachof the one or more openings, the respective size for each of the one ormore openings, or the respective location in the second magnetic layerfor each of the one or more openings.

In a fourth implementation, alone or in combination with one or more ofthe first through third implementations, the one or more performanceparameters include a maximum inductance for the inductive device. In afifth implementation, alone or in combination with one or more of thefirst through fourth implementations, the one or more performanceparameters include a saturation current for the inductive device. In asixth implementation, alone or in combination with one or more of thefirst through fifth implementations, a shape for an opening of the oneor more openings includes a trench, and a size for the opening includesa length parameter for the trench and a width parameter for the trench.

Although FIG. 6 shows example blocks of process 600, in someimplementations, process 600 may include additional blocks, fewerblocks, different blocks, or differently arranged blocks than thosedepicted in FIG. 6 . Additionally, or alternatively, two or more of theblocks of process 600 may be performed in parallel.

In this way, an inductive device (e.g., inductive device 100) includesan insulating layer (e.g., insulating layer 102), a lower magnetic layer(e.g., lower magnetic layer 108 a), and an upper magnetic layer (e.g.,upper magnetic layer 108 b) that are formed such that the insulatinglayer does not separate the lower magnetic layer and the upper magneticlayer at the outer edges of the inductive device. The lower magneticlayer and the upper magnetic layer form a continuous magnetic layeraround the insulating layer and the conductors of the inductive device.Magnetic leakage paths are provided for the inductive device by formingopenings (e.g., opening(s) 110) in the upper magnetic layer instead ofthrough the formation of the insulating layer. The openings are formedin the upper magnetic layer by semiconductor processes that haverelatively higher precision and accuracy compared to semiconductorprocesses for forming the insulation layer such as spin coating. Thisreduces magnetic leakage path variation within the inductive device andfrom inductive device to inductive device. Moreover, the performancecharacteristics of the inductive device can be tuned based on theattributes of the openings in the upper magnetic layer to achievedesired and/or optimal inductor performance.

As described in greater detail above, some implementations describedherein provide an inductive device. The inductive device includes one ormore insulating layers, one or more conductors, a lower magnetic layer,and an upper magnetic layer. The lower magnetic layer contacts the uppermagnetic layer in one or more edges or one or more wings of theinductive device such that a continuous magnetic layer is formed in theone or more edges or the one or more wings. The lower magnetic layer andthe upper magnetic layer surround the one or more insulating layers andthe one or more conductors, except for one or more openings through atleast one of the upper magnetic layer or through the lower magneticlayer that provide one or more magnetic leakage paths for the inductivedevice.

As described in greater detail above, some implementations describedherein provide a method. The method includes removing one or moreportions of a first insulating layer of an inductive device from a firstmagnetic layer of the inductive device. The method includes forming asecond magnetic layer of the inductive device on one or more portions ofthe first magnetic layer where the one or more portions of the firstinsulating layer were removed. The second magnetic layer is formed overthe first insulating layer, a second insulating layer of the inductivedevice, and one or more conductors of the inductive device. The methodincludes removing one or more portions of the second magnetic layer toform one or more openings in the second magnetic layer. The one or moreopenings provide one or more magnetic leakage paths for the inductivedevice.

As described in greater detail above, some implementations describedherein provide an inductive device. The inductive device includes alower magnetic layer, a first insulating layer on a portion of the lowermagnetic layer, one or more conductors on the first insulating layer, asecond insulating layer over the first insulating layer and the one ormore conductors, and an upper magnetic layer on the second insulatinglayer and contacting portions of the lower magnetic layer in one or moreedges or one or more wings of the inductive device. One or more openingsare formed through the upper magnetic layer and to the second insulatinglayer to provide one or more magnetic leakage paths for the inductivedevice. The one or more openings are based on one or more performanceparameters for the inductive device.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A method, comprising: forming a first magneticlayer on one or more portions, of a second magnetic layer, that are overone or more insulating layers and one or more conductors; and removingone or more portions, of the first magnetic layer, to form one or moreopenings in the first magnetic layer.
 2. The method of claim 1, whereinthe second magnetic layer has a first insulating layer, of the one ormore insulating layers, on at least a portion of a surface of the secondmagnetic layer.
 3. The method of claim 1, wherein removing the one ormore portions of the first magnetic layer comprises: forming aphotoresist layer on the first magnetic layer; patterning thephotoresist layer; and etching, after patterning the photoresist layer,the one or more portions of the first magnetic layer.
 4. The method ofclaim 1, further comprising: forming the one or more conductors on afirst insulating layer of the one or more insulating layers, forming asecond insulating layer, of the one or more insulating layers, on thefirst insulating layer and the one or more conductors; and forming thefirst magnetic layer to cover the second insulating layer and the one ormore portions of the second magnetic layer.
 5. The method of claim 1,wherein removing the one or more portions of the first magnetic layercomprises: determining, based on one or more performance parameters foran inductive device, at least one of: a respective shape for each of theone or more openings, a respective size for each of the one or moreopenings, or a respective location in the first magnetic layer for eachof the one or more openings; and removing the one or more portions ofthe first magnetic layer to form the one or more openings based on theat least one of: the respective shape for each of the one or moreopenings, the respective size for each of the one or more openings, orthe respective location in the first magnetic layer for each of the oneor more openings.
 6. The method of claim 5, wherein the one or moreperformance parameters include at least one of a maximum inductance forthe inductive device or a saturation current for the inductive device.7. The method of claim 5, wherein a shape of an opening of the one ormore openings includes a trench; and wherein a size of the openingincludes a length parameter of the trench, a width parameter of thetrench, and a depth parameter of the trench.
 8. A method, comprising:forming a first insulating layer on a first magnetic layer; forming aconductive layer on the first insulating layer; forming a secondinsulating layer over the conductive layer, forming a second magneticlayer on the second insulating layer and one or more portions of thefirst magnetic layer; and forming one or more openings through thesecond magnetic layer.
 9. The method of claim 8, further comprising:removing, based on forming the second insulating layer, one or moreportions of the second insulating layer, wherein the one or moreopenings are formed via the one or more portions removed from the secondinsulating layer.
 10. The method of claim 9, wherein the one or moreportions of the second insulting layer are removed via a patternedphotoresist layer.
 11. The method of claim 8, wherein the conductivelayer is formed via at least one of: a chemical vapor depositionprocess, a physical vapor deposition process, or a plating process. 12.The method of claim 8, wherein the conductive layer is formed via apatterned photoresist layer.
 13. The method of claim 8, wherein thesecond insulating layer is further formed on one or more portions of thefirst insulating layer.
 14. A method, comprising: forming a firstmagnetic layer on a first insulating layer, a second insulating layer,and a second magnetic layer, wherein the first insulating layer and thesecond insulating layer encapsulate one or more conductors; and formingone or more openings through the second magnetic layer and over the oneor more conductors.
 15. The method of claim 14, further comprising:forming a photoresist layer on the first magnetic layer, wherein the oneor more openings are formed via a pattern of the photoresist layer; andremoving the photoresist layer.
 16. The method of claim 14, wherein theone or more openings are a plurality of holes.
 17. The method of claim16, wherein the one or more holes are a single trench.
 18. The method ofclaim 14, wherein forming the one or more openings comprises:determining, based on one or more performance parameters for aninductive device, at least one of: a respective shape for each of theone or more openings, a respective size for each of the one or moreopenings, or a respective location in the first magnetic layer for eachof the one or more openings; and forming the one or more openings basedon the at least one of: the respective shape for each of the one or moreopenings, the respective size for each of the one or more openings, orthe respective location in the first magnetic layer for each of the oneor more openings.
 19. The method of claim 18, wherein the one or moreperformance parameters includes a maximum inductance for the inductivedevice.
 20. The method of claim 18, wherein the one or more performanceparameters includes a saturation current for the inductive device.